Associated with the rapid progress of semiconductor integration circuit techniques and the development of a higher integration of semiconductor elements, a technological revolution for semiconductor memory devices has been in progress with the aim of gaining larger capacity and further miniaturization.
A data read operation performed in a memory device requires pre-charging the data lines, which are commonly referred to in conventional flash devices as “bit lines” (in light of this convention, the term “bit lines” will be used hereinafter in the examples). The reason is that, to confirm whether a memory cell is in an erase state “1” or program state “0”, a verification of a change in potential is difficult unless the bit line is provided with a certain level of potential. A common practice is to apply a pre-charge voltage to increase the voltage of the bit line to a predetermined value in advance, followed by detecting a change in the voltage of the bit line when the bit line is applied to a memory cell by comparing the voltage of the bit line with the pre-charge voltage used as a reference.
One recent problem accompanying large capacity memory (on the order of gigabytes) is the extension of the length of bit lines. This causes the resistance value R of the bit line to increase and the parasitic capacitance C between the bit lines to increase, thus increasing a time constant RC of the bit lines. An increase in the time constant RC results in increasing the time period required to drive the bit lines to a voltage, for example, to a pre-charge voltage. Because pre-charging of bit lines is performed for most memory access operations, and increase in the time to pre-charge bit lines may be significant and have a negative effect on memory performance.